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    SYSTEM AND METHOD FOR CONTROLLING THE ENERGY OF CENTRAL PROCESSING UNIT BASED ON PARALLELISM OF INFERENCED WORKLOAD. A method of dynamic power control within a multi-core CPU is described and may include receiving a degree of parallelism in a zero-core workload and determining whether the degree of parallelism in the zero-core workload is equal to a first active condition. Additionally, the method may include determining a length of time for which the first active condition is satisfied when the degree of parallelism in the zero core workload is equal to the first active condition and determining whether the time duration is equal to a first active condition confirmed. The method can also include invoking an operating system to power a first core when the time duration is equal to the first confirmed active condition.
    公开号:BR112012014308B1
    申请号:R112012014308-5
    申请日:2010-11-24
    公开日:2021-01-19
    发明作者:Bohuslav Rychlik；Robert A. Glenn；Ali Iranli；Brian J. Salsbery；Sumit Sur；Steven S. Thomson
    申请人:Qualcomm Incorporated；
    IPC主号:
    专利说明:

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    [0001] The present application claims priority of provisional patent application US No. 61 / 286,953, entitled “SYSTEM AND METHOD OF DYNAMICALLY CONTROLLING A PLURALITY OF CORES IN A MULTICORE CENTRAL PROCESSING UNIT”, filed on December 16, 2009, the content being fully incorporated by reference. Description of the Prior Art
    [0002] Portable computing devices (PCDs) are ubiquitous. These devices can include cell phones, portable digital assistants (PDAs), handheld game consoles, palmtop computers, and other portable electronic devices. In addition to the primary function of these devices, they may include peripheral functions. For example, a cell phone may include the primary function of making cell phone calls and the peripheral functions of a static camera, a video camera, global positioning system (GPS) navigation, network navigation, sending and receiving e- email, send and receive text messages, press-to-speak capabilities, etc. As the functionality of such a device increases, the processing power required to support such functionality also increases. Additionally, as computing power increases, there is a greater need to effectively manage the processor, or processors, that provide computing power.
    [0003] Accordingly, what is needed is an improved method to control the energy inside a multi-core CPU. Brief Description of Drawings
    [0004] In the figures, similar numerical references refer to similar parts by all views unless otherwise indicated.
    [0005] Figure 1 - is a front plan view of a first aspect of a portable computing device (PCD) in a closed position.
    [0006] Figure 2 - is a front plan view of the first aspect of a PCD in an open position.
    [0007] Figure 3 - is a block diagram of a second aspect of a PCD.
    [0008] Figure 4 - is a block diagram of a processing system.
    [0009] Figure 5 - is a flowchart illustrating a first aspect of a method for dynamic energy control within a multi-core CPU.
    [0010] Figure 6 - is a flowchart illustrating a second aspect of a method for dynamic energy control within a multi-core CPU.
    [0011] Figure 7 - is a flowchart illustrating a third aspect of a method for dynamic energy control within a multi-core CPU.
    [0012] Figure 8 - is a flowchart illustrating a fourth aspect of a method for dynamic energy control within a multi-core CPU.
    [0013] Figure 9 - is a flowchart illustrating a first part of a fifth aspect of a method for dynamic energy control within a multi-core CPU.
    [0014] Figure 10 - is a flowchart illustrating a second part of a fifth aspect of a method for controlling dynamic energy within a multi-core CPU.
    [0015] Figure 11 - is a flowchart illustrating a third part of a fifth aspect of a method for dynamic energy control within a multi-core CPU.
    [0016] Figure 12 - is a flowchart illustrating a fourth part of a fifth aspect of a method for dynamic energy control within a multi-core CPU.
    [0017] Figure 13 - is a flowchart illustrating a method of testing a multi-core CPU.
    [0018] Figure 14 - is a flowchart illustrating a sixth aspect of a method for controlling dynamic energy within a multi-core CPU. Detailed Description of the Invention
    [0019] The term "illustrative" is used here to mean "serving as an example, case or illustration". Any aspect described here as "illustrative" should not necessarily be considered, as preferred or advantageous over other aspects.
    [0020] In this description, the term "application" can also include files containing executable content, such as: object code, scripts, byte code, markup language files, and amendments. In addition, an "application" referred to here, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
    [0021] The term "content" can also include files containing executable content, such as: object code, scripts, byte code, markup language files, and amendments. In addition, "content" as referred to here, may also include files that are not executable in nature, such as documents that need to be opened or other data files that need to be accessed.
    [0022] As used in this description, the terms "component", "database", "module", "system" and the like must refer to a computer-related entity, ie, hardware, firmware, a combination of hardware and software, software, or running software. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a chain of execution, a program and / or a computer. By way of illustration, both an application running on a computer device and the computer device can be a component. One or more components can reside within a process and / or sequence of execution, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having several data structures stored therein. Components can communicate via local and / or remote processes such as according to a signal having one or more data packets (for example, data from a component interacting with other components in a local system, distributed system, and / or over a network such as the Internet with other systems using a signal).
    [0023] With reference initially to Figure 1 and Figure 2, an illustrative portable computing device (PCD) is illustrated and is generally referred to as 100. As illustrated, PCD 100 may include a housing 102. Housing 102 may include a upper part of the housing 104 and a lower part of the housing 106. Figure 1 illustrates that the upper part of the housing 104 can include a screen 108. In a particular aspect, the screen 108 can be a touch screen. The upper part of the housing 104 can also include a trackball type 110 input device. Additionally, as illustrated in Figure 1, the upper part of the housing 104 can include a power button 112 and an power button 114. As shown in Figure 1, the upper part of the housing 104 of the PCD 100 may include a plurality of indicator lights 116 and a speaker 118. Each indicator light 116 may be a light emitting diode (LED).
    [0024] In a particular aspect, as shown in Figure 2, the upper part of the housing 104 is movable with respect to the lower part of the housing 106. Specifically, the upper part of the housing 104 can be slidable with respect to the lower part of the housing 106 As illustrated in Figure 2, the bottom of housing 106 may include a multi-button keyboard 120. In a particular aspect, the multi-button keyboard 120 may be a standard QWERTY keyboard. The multi-button keypad 120 can be revealed when the upper part of the housing 104 is moved with respect to the lower part of the housing 106. Figure 2 also illustrates that the PCD 100 can include a reset button 122 at the bottom of the housing 106.
    [0025] With reference to Figure 3, an illustrative non-limiting aspect of a PCD is illustrated and is generally referred to as 320. As illustrated, PCD 320 includes an on-chip system 322 that includes a multi-core CPU 324. The CPU multi-core 324 can include a zero core 325, a first core 326, and a Nésimo327 core.
    [0026] As illustrated in Figure 3, a display controller 328 and a touchscreen controller 330 are coupled to the multi-core CPU 324. In turn, a display / touchscreen 332 external to the on-chip system 322 is coupled to the display controller 328 and the touchscreen controller 330.
    [0027] Figure 3 also indicates that a 334 video encoder, for example, an alternating phase line encoder (PAL), a sequential memory encoder (SECAM), or an encoder for the national television systems committee (NTSC) ), is coupled to the multi-core CPU 324. Additionally, a video amplifier 336 is coupled to the video encoder 334 and the display / touchscreen 332. In addition, a video port 338 is coupled to the video amplifier 336 As shown in Figure 3, a universal serial bus (USB) controller 340 is attached to the multi-core CPU 324. In addition, a USB port 342 is attached to the USB controller 340. A 344 memory and an identity module card (SIM) number 346 can also be coupled to the multi-core CPU 324. Additionally, as illustrated in Figure 3, a digital camera 348 can be coupled to the multi-core CPU 324. In an illustrative aspect, the digital camera 348 is a disp camera load-coupled oscillator (CCD) or a complementary metal oxide semiconductor (CMOS) camera.
    [0028] As also illustrated in Figure 3, a stereo audio CODEC 350 can be coupled to the multi-core CPU 324. Furthermore, an audio amplifier 352 can be coupled to the stereo audio CODEC 350. In an illustrative aspect, a first stereo speaker 354 and a second stereo speaker 356 are coupled to the audio amplifier 352. Figure 3 illustrates that a microphone amplifier 358 can also be coupled to the stereo audio CODEC 350. Additionally, a microphone 360 can be coupled to the amplifier microphone 358. In a particular aspect, a frequency modulation (FM) radio tuner 362 can be coupled to the stereo audio CODEC 350. In addition, an FM antenna 364 is coupled to the FM radio tuner 362. Additionally, headphones stereo earphones 366 can be coupled to the stereo audio CODEC 350.
    [0029] Figure 3 also indicates that a radio frequency (RF) transceiver 368 can be coupled to the multi-core CPU 324. An RF switch 370 can be coupled to the RF transceiver 368 and an RF antenna 372. As illustrated in Figure 3, a keyboard 374 can be coupled to the multi-core CPU 324. In addition, a mono headset with a microphone 376 can be coupled to the multi-core CPU 324. Additionally, a vibrating device 378 can be coupled to the multi-core CPU 324. Figure 3 also illustrates that a power supply 380 can be coupled to the on-chip system 322. In one particular aspect, the power supply 380 is a direct current (DC) power supply ) that supplies power to the various components of the PCD 320 that require power. Additionally, in a particular aspect, the power supply is a rechargeable DC battery or a DC power source that is derived from an alternating current (AC) to DC transformer that is connected to an AC power source.
    [0030] Figure 3 also indicates that PCD 320 can also include a 388 network card that can be used to access a data network, for example, a local area network, a personal area network, or any other network . The 388 network card can be a Bluetooth network card, a WiFi network card, a personal area network card (PAN), a personal area network ultra low power technology network card (PeANUT), or any other network card well known in the art. In addition, network card 388 can be incorporated into a chip, that is, network card 388 may be a complete solution on a chip, and may not be a separate network card 388.
    [0031] As shown in Figure 3, the display / touch screen 332, the video port 338, the USB port 342, the camera 348, the first stereo speaker 354, the second stereo speaker 356, the microphone 360 , the FM antenna 364, the stereo headphones 366, the RF switch 370, the RF antenna 372, the keyboard 374, the mono headset 376, the vibrator 378, and the power supply 380 are external to the system on-chip 322.
    [0032] In one particular aspect, one or more steps of the method described here can be stored in memory 344 as computer program instructions. These instructions can be executed by the multicore CPU 324 in order to carry out the methods described here. In addition, the multi-core CPU 324, memory 344, or a combination of these can serve as a means to perform one or more of the method steps described here in order to control the power for each CPU, or core, within the CPU. multiple cores 324.
    [0033] With reference to Figure 4, a processing system is illustrated and is generally referred to as 400. In a particular aspect, the processing system 400 can be incorporated into the PCD 320 described above in conjunction with Figure 3. As illustrated, the processing system 500 may include a multi-core central processing unit (CPU) 402 and a memory 404 connected to the multi-core CPU 402. The multi-core CPU 402 may include a zero core 410, a first core 412, and a Nésimo nucleus414. Core zero 410 may include a voltage scaling algorithm and dynamic zero clock (DCVS) 416 running on it. The first core 412 may include a first DCVS algorithm 417 executed therein. Additionally, the Nésimo414 kernel can include a DCVS Nésimo418 algorithm running on it. In a particular aspect, each DCVS 416, 417, 418 algorithm can be run independently on a respective core 410, 412, 414.
    [0034] Furthermore, as illustrated, memory 404 may include an operating system 420 stored therein. The operating system 420 may include a programmer 422 and programmer 422 may include a first execution row 424, a second execution row 426, and a Nésimafil from execution 428. Memory 404 may also include a first application 430, a second application 432, and a Nth application 434 stored in it.
    [0035] In a particular aspect, the application 430, 432, 434 can send one or more tasks 436 to the operating system 420 to be processed in cores 410, 412, 414 within the multi-core CPU 402. Tasks 436 can be processed, or executed, as single tasks, sequences, or a combination of these. In addition, programmer 422 can program tasks, sequences, or a combination of them to run within the multi-core CPU 402. Additionally, programmer 422 can place tasks, sequences, or a combination of them in execution queues 424, 426, 428. Cores 410, 412, 414 can retrieve tasks, sequences or a combination of them from execution queues 424, 426, 428, as instructed, for example, by operating system 420 for processing, or execution, of these tasks and sequences in cores 410, 412, 414.
    [0036] Figure 4 also illustrates that memory 404 may include a parallelism monitor 440 and a multicore processor controller (MP) 442 stored therein. Parallelism monitor 440 can be connected to operating system 420 and controller MP 442. Specifically, parallelism monitor 440 can be connected to programmer 422 within operating system 420. As described here, parallelism monitor 440 can monitor load working in cores 410, 412, 414 and the MP 442 controller can control the power for cores 410, 412, 414, as described below. In a particular aspect, when executing one or more of the method steps, for example, as computer program instructions, described here, the parallelism monitor 440, the MP controller 442, or a combination thereof can serve as a means to dynamically control power to cores 410, 412, 414 within the multi-core CPU 402.
    [0037] In a particular dual-core aspect, during operation, the MP 442 controller can receive information from the 440 parallelism monitor. The information can be a total system load. Furthermore, the information can be an average of the degree of parallelization in the workload. Based on the information, the MP 442 controller can determine whether a single core or two cores should be powered. In addition, the MP 442 controller can send a control signal to the multi-core CPU 402. The control signal can indicate whether to turn the additional cores on or off. In the dual-core example, the MP 442 controller can include four threshold values to control the decision to turn the cores on or off. The four limit values can include a number of ready-to-run strings in the OS programmer's queue to trigger an active kernel, Nw; a length of time for which the Nw has been exceeded to confirm the inactivity of the nucleus, Tw; a number of ready-to-run sequences in the OS programmer to trigger an inactive core, Ns; and a length of time for which the Ns has been exceeded to confirm the inactivity of the nucleus, Ts.
    [0038] Starting with a single active core, for example, the zero core 410, when the average execution of the degree of parallelism in the zero core 410 workload corresponds to or exceeds Nw for a duration of at least Tw, the controller of MP 442 can wake up a second core, for example, the first core 412. Conversely, when both cores, for example, the zero core 410 and the first core 412, are active and when the degree of parallelism in the workload falls below Ns for at least a duration of Ts, the MP controller 442 may decide to put the second nucleus, for example, the first nucleus 412, at rest.
    [0039] In a particular aspect, the limit parallelism sustained through time Tw implies that the single nucleus is saturated. In addition, the cores can be started at the most energy-efficient (VF) frequency and voltage operating point. In a particular aspect, two cores operating at an ideal VF offer more than one million Dhrystone instructions per second (DMIPS) than a single core operating at a maximum VF. In a dual-core aspect, two independent DCVS algorithms can adapt asymmetric workloads and in some cases, heterogeneous cores. In addition, in a dual-core aspect, the two cores must remain active during multi-task workloads in order to avoid a double performance penalty. In addition, when the parallelism falls below Ns for the prescribed time Ts, the second core must be de-energized and not put on hold. In a particular aspect, placing the second core on hold can increase energy leakage and can also reduce performance.
    [0040] The ideal values of the parameters, Nw, Tw, Ns, and Ts may depend on the exact power consumption characteristics of the 400 system. However, in one aspect, the values can be as follows: Nw = 1,2 ; Tw = 40 milliseconds (ms); Ns = 0.8; and Ts = 80 ms.
    [0041] In this particular aspect, Nw = 1,2 can ensure sustained parallelism before the second core is agreed. Ns = 0.8 can ensure a sustained absence of parallelism before the second core is put to rest. Ts = 80 ms is based on a system power collapse limit, 400 ms. Tw = 40 ms is half of Ts to improve the response to multiple cores.
    [0042] Figure 5 illustrates a first aspect of a method for controlling energy within a multi-core processor. The method is generally referred to as 500. Method 500 starts at block 502 with the initialization of the circuit in which, during operation, a device having a multi-core processor, the successive steps can be performed. In block 504, a power controller can dynamically infer a degree of workload parallelism within the CPUs, or cores, for example, when monitoring an operating system state. Moving to block 506, at least partially based on the degree of workload parallelism, the power controller can turn the cores on or off. In other words, the power controller can turn the cores on or off based on the workload.
    [0043] In decision 508, the power controller can determine whether the device is turned off. If the device is turned off, the method can be terminated. Otherwise, if the device remains on, method 500 can return to block 504 and method 500 can continue as described.
    [0044] Referring now to Figure 6, a second aspect of a method for controlling energy within a multi-core processor is illustrated and is generally referred to as 600. Method 600 begins at block 602 with the initialization of the circuit in which during operation of a device having a multi-core processor, successive steps can be performed. In block 604, a controller, for example, a parallelism monitor, can monitor the length of all ready-to-run queues of the OS programmer in order to determine a degree of workload parallelism within the CPUs, or cores. In a particular aspect, the parallelism monitor can be a software program residing in a device memory. Additionally, in a first aspect, the programmer's ready-to-run queue is a list of current sequence tasks that are available for programming on one or more CPUs. Some multicore systems may have only a single ready-to-run queue. rotate. Other multi-core systems can have multiple ready-to-run queues. Regardless of the number of ready-to-run queues at any one time, the total number of tasks, sequences, or a combination of these waiting in these queues, plus a number of tasks, sequences, or a combination of these currently running, can be an approximation of degree of parallelism in the workload.
    [0045] Moving to block 606, at least partially based on the degree of workload parallelism, the parallelism monitor can turn the cores on or off. In other words, the parallelism monitor can turn the cores on or off based on the workload.
    [0046] In decision 608, the parallelism monitor can determine if the device is turned off. If the device is turned off, the method can be terminated. Otherwise, if the device remains on, method 600 can return to block 604 and method 600 can continue as described.
    [0047] Referring to Figure 7, a third aspect of a method for controlling energy within a multi-core processor is illustrated and is generally referred to as 700. Method 700 begins at block 702 with the initialization of the circuit in which during operation of a device having a multi-core processor, successive steps can be performed. In block 704, a parallelism monitor can periodically sample a ready-to-run queue length. For example, the parallelism monitor can sample the ready-to-run queue length every millisecond (1 ms). In block 706, the parallelism monitor can determine an execution average of the degree of parallelism in the workload. Move to block 708, at least partially based on the degree of workload parallelism, the parallelism monitor can turn the cores on or off. In other words, the parallelism monitor can turn the cores on or off based on the workload.
    [0048] In decision 710, the parallelism monitor can determine whether the device is turned off. If the device is turned off, the method can be terminated. Otherwise, if the device remains on, method 700 can return to block 704 and method 700 can continue as described.
    [0049] Figure 8 presents a fourth aspect of a method for controlling energy within a multi-core processor. The method is generally referred to as 800 and method 800 begins at block 802 with circuit initialization in which, during operation, a device having a multi-core processor, the successive steps can be performed. In block 804, a parallelism monitor can receive a callback from the operating system (OS) whenever information is added to or removed from the OS programmer's execution queue. Additionally, in block 806, the parallelism monitor can determine an average of the degree of parallelism in the workload of the CPUs, or cores.
    [0050] Move to block 808, at least partially based on the degree of workload parallelism, the parallelism monitor can turn the cores on or off. In other words, the parallelism monitor can turn the cores on or off based on the workload. In decision 810, the parallelism monitor can determine whether the device is turned off. If the device is turned off, the method can be terminated. Otherwise, if the device remains on, method 800 can return to block 804 and method 800 can continue as described.
    [0051] Referring now to Figures 9 to 12, a fifth aspect of a method for controlling energy within a multi-core processor is illustrated and is generally referred to as 900. Method 900 begins at block 902 with the circuit initializing at which when a device having a multi-core processor is powered up, the following steps can be performed. In block 904, a zero core can be connected, that is, energized. In block 905, a DCVS zero algorithm can be executed locally at the zero core. Additionally, in block 906, one or more tasks, or sequences, can be performed at the zero core.
    [0052] Moving to decision 908, a multi-core processor (MP) controller can determine whether the device is turned off. If so, method 900 can be terminated. Otherwise, if the device remains on, method 900 can move to block 910 and the MP controller can receive an average execution degree of parallelism in the zero core workload from a parallelism monitor. In a particular aspect, at any given time, the total number of tasks, sequences, or a combination of these, waiting in the ready-to-run queues of an operating system (OS) plus the number of tasks currently running can be an approximation of degree of parallelism in the core workload.
    [0053] In decision 912, the PM controller can determine whether the degree of parallelism is equal to a first awakening condition. In a particular aspect, the first awakening condition can be a threshold value associated with the degree of parallelism in the core workload. For example, the threshold value can be a predetermined number of ready-to-run sequences in the OS programmer queues and if the parallelism is greater than or equal to this threshold value, the first awakening condition can be satisfied.
    [0054] Returning to decision 912, if the degree of parallelism is not equal to a first awakening condition, method 900 can return to block 910 and method 900 can continue as described here. Otherwise, if the degree of parallelism is equal to a first wake-up condition, method 900 can move to block 914 and the PM controller can determine a length of time for the first wake-up condition to be satisfied. In decision 916, the PM controller can determine whether the time duration is equal to a first confirmed wake-up condition. In a particular aspect, the first confirmed awakening condition can be a timeout value and if the length of time for which the first awakening condition is greater than or equal to the limit value, the first confirmed awakening condition can be satisfied .
    [0055] Returning to decision 916, if the length of time for which the first awakening condition is met is not equal to a first confirmed awakening condition, method 900 can return to block 910 and method 900 can continue as described here. Conversely, if the first confirmed awakening condition is met, method 900 can move to block 918 and the MP controller can invoke the OS to energize a first core so that two cores, that is, the zero core and the first core, are running and executing sequences and tasks. In block 920, the MP controller can invoke the OS to add the first core to a set of programmable features available to the OS. Additionally, in block 922, a first DCVS algorithm can be executed locally in the first core. After that, method 900 can proceed to block 1002 of Figure 10.
    [0056] Moving now to the block 1002 of Figure 10, one or more tasks, sequences or a combination of these can be performed in the zero core and in the first core. In decision 1004, an MP controller can determine whether the device is turned off. If so, method 900 can be terminated. Otherwise, if the device remains on, method 900 can move to block 1006 and the MP controller can receive an average execution degree of degree of parallelism in the workload at the zero core and the first core from the parallelism monitor . In a particular aspect, at any time, the total number of tasks, sequences or a combination of these, waiting in the ready-to-run queues of an operating system (OS) plus the number of tasks currently running can be an approximation to the degree of parallelism in the workload in the cores.
    [0057] In decision 1008, the MP controller can determine whether the degree of parallelism is equal to a first rest condition. In a particular aspect, the first resting condition can be a limit value associated with the degree of parallelism in the workload in the core. For example, the limit value can be a minimum number of ready-to-run strings in the OS programmer queues and if the parallelism is less than or equal to this limit value, the first rest condition can be satisfied.
    [0058] Returning to decision 1008, if the degree of parallelism is not equal to the first resting condition, method 900 can proceed to block 1102 of Figure 11 and method 900 can continue as described here. Otherwise, if the degree of parallelism is equal to the first rest condition, method 900 can move to block 1010 and the MP controller can determine a length of time for the first rest condition to be satisfied. In decision 1012, the PM controller can determine whether the length of time is equal to a first confirmed resting condition. In a particular aspect, the first confirmed rest condition can be a timeout value and if the length of time for which the first rest condition is greater than or equal to the limit value, the first confirmed rest condition can be satisfied .
    [0059] Returning to decision 1012, if the length of time for which the first resting condition is satisfied is not equal to a first confirmed resting condition, method 900 can proceed to block 1102 of Figure 11 and the method 900 can continue as described here. Conversely, if the first confirmed resting condition is satisfied, method 900 can move to block 1014 and the MP controller can invoke the OS to save a current state of the first core. In block 1016, the MP controller can invoke the OS to de-energize the first core so that a core, that is, the zero core, is running and executing sequences and tasks. Additionally, at block 1018, the MP controller can invoke the OS to remove the first kernel from the set of programmable features available to the OS. After that, method 900 can return to block 906 of Figure 9 and method 900 can continue as described here.
    [0060] With reference now to Figure 11, in block 1102, the MP controller can receive an average of the degree of parallelism in the workload in the zero core and the first core from the parallelism monitor. In a particular aspect, at any given time, the total number of tasks, sequences or a combination of these, waiting in the ready-to-run queues of an operating system (OS) plus the number of tasks currently running can be an approximation to the degree of parallelism in the workload in the cores. In decision 1104, the PM controller can determine whether the degree of parallelism is equal to a Nésima awakening condition. In a particular aspect, the Nésima awakening condition can be a limit value associated with the degree of parallelism in the workload in the cores. For example, the limit value can be a maximum number of ready-to-run strings in the OS programmer's queues and if the parallelism is greater than or equal to this limit value, the Nésima awakening condition can be satisfied.
    [0061] Returning to decision 1104, if the degree of parallelism is not equal to the Nésima awakening condition, method 900 can return to block 1002 of Figure 10 and method 900 can continue as described here. Otherwise, if the degree of parallelism is equal to the Nésima awakening condition, method 900 can move to block 1106 and the PM controller can determine a length of time for which the Nésima awakening condition is satisfied. In decision 1108, the PM controller can determine whether the time duration is equal to a confirmed Nésima wake-up condition. In a particular aspect, the confirmed Nésima awakening condition can be a timeout value and if the length of time for which the Nésima awakening condition is greater than or equal to the limit value, the confirmed Nésima awakening condition can be satisfied.
    [0062] Return to decision 1108, if the length of time for which the Nésima awakening condition is satisfied is not equal to the confirmed Nésima awakening condition, method 900 can return to block 1002 of Figure 10 and method 900 can continue as described here. Conversely, if the confirmed Nésima awakening condition is satisfied, method 900 can move to block 1110 and the MP controller can invoke the OS to energize a Nésima nucleus so that N nuclei, that is, the zero nucleus, the first nucleus and the Nésima core, are running and executing sequences and tasks. In block 1112, the MP controller can invoke the OS to add the Nésimaa core to a set of programmable features available to the OS. Additionally, in block 1114, a DCVS Nésima algorithm can be executed locally in the Nésima nucleus. Therefore, method 900 can proceed to block 1202 of Figure 12.
    [0063] In block 1202 of Figure 12, one or more tasks, sequences or a combination of these can be performed on the zero core, the first core and the Nth nucleus. In decision 1204, an MP controller can determine whether the device is turned off. If so, method 900 can be terminated. Otherwise, if the device remains on, method 900 can move to block 1206 and the MP controller can receive an average execution degree of parallelism in the workload in the zero core, in the first core, and in the Nésimo core from of the parallelism monitor. In a particular aspect, at any given time, the total number of tasks, sequences, or a combination of these, waiting in the ready-to-run queues of an operating system (OS) plus the number of tasks currently running can be an approximation for the degree of parallelism in the workload in the cores.
    [0064] In decision 1208, the PM controller can determine whether the degree of parallelism is equal to a Nésima rest condition. In a particular aspect, the Nésima rest condition can be a limit value associated with the degree of parallelism in the core workload. For example, the limit value can be a minimum number of ready-to-run sequences in the OS programmer's queues and if the parallelism is less than or equal to this limit value, the Nésima rest condition can be satisfied.
    [0065] Returning to decision 1208, if the degree of parallelism is not equal to the Nésima resting condition, method 900 can proceed to block 1202 and method 900 can continue as described here. Otherwise, if the degree of parallelism is equal to the Nésima rest condition, method 900 can move to block 1210 and the PM controller can determine a length of time for which the Nésima rest condition is satisfied. In decision 1212, the PM controller can determine whether the time duration is equal to a confirmed Nésima rest condition. In a particular aspect, the confirmed Nésima rest condition can be a timeout value and if the length of time for which the Nésima rest condition is greater than or equal to a limit value, the Nésima confirmed rest condition can be satisfied.
    [0066] Returning to decision 1212, if the length of time for which the Nésimafor rest condition is satisfied is not equal to the confirmed Nésima rest condition, method 900 can return to block 1202 and method 900 can continue as described on here. Conversely, if the Nésima confirmed resting condition is satisfied, method 900 can move to block 1214 and the MP controller can invoke the OS to save a current state of the first core. In block 1216, the MP controller can invoke the OS to shut down the Nth core so that N minus a few cores, for example, the zero core, and the first core (if N is 2 and a second core is off), are running and running sequences and tasks. Additionally, at block 1218, the MP controller can invoke the OS to remove the core Nésimodo set of programmable features available to the OS. After that, method 900 can return to block 1002 of Figure 10 and method 900 can continue as described here.
    [0067] Referring now to Figure 13, a test method for a multi-core processor is illustrated and is generally referred to as 1300. As illustrated, method 1300 can start at block 1302 where a test program can be created. The test program can include a steady-state workload with varying degrees of parallelism that would cause a plurality of cores to energize and de-energize depending on the degree of parallelism, as described here.
    [0068] Moving to block 1304, the test program can be loaded on a wireless device that includes a multi-core processor. In block 1306, a plurality of cores can be monitored on the wireless device. For example, the on / off status of the core for each core can be monitored. The on / off state can be monitored by monitoring the energy in each core, by monitoring the total energy consumed, the speed at which workloads are completed, or a combination of these.
    [0069] In block 1308, the test program can be run on the wireless device. Furthermore, in Decision 1310, it can be determined whether the cores within the wireless device respond correctly to the execution of the test program. In other words, it can be determined whether the cores are being energized / de-energized correctly in response to the execution of the test program. In decision 1310, if the cores do not respond correctly to the execution of the test program, method 1300 can move to block 1312 and a failure result can be indicated. The 1300 method can then be terminated.
    [0070] In decision 1310, if the cores do not respond correctly to the execution of the test program, the method can proceed to block 1314 and a positive result can be indicated. After that, method 1300 can be terminated.
    [0071] Figure 14 illustrates a sixth aspect of a method for dynamic power control within a multi-core CPU. The method is generally referred to as 1400. Starting at block 1402, a controller can determine a run queue value for a zero core. The execution queue value can indicate the workload for the zero core. In block 1404, the controller can determine an operating frequency for the zero core. In addition, in block 1406, the controller can determine a percentage of utilization for the zero core. In a particular aspect, the utilization percentage for the zero core can be the current operating frequency divided by the maximum operating frequency for the zero core. In block 1408, the controller can determine an inactive percentage for the zero core.
    [0072] By moving to block 1410, the controller can determine a value of the execution queue for a Nésimo core. In block 1412, the controller can determine an operational frequency for the Nésimo core. Additionally, in block 1414, the controller can determine a utilization percentage for the Nésimo core. In block 1416, the controller can determine an inactive percentage for the Nésimo core.
    [0073] By moving to block 1418, the controller can determine a load value for the system. The load value can be determined based on the execution queue value for the zero core, the execution queue value for the Nésimo core, the operating frequency of the zero core, the operating frequency of the Nésimo core, the percentage of use of the nucleus Nésimo, the percentage of utilization of the nucleus Nésimo, the percentage inactive for the nucleus zero, the percentage inactive for the nucleus Nésimo, or any combination of these.
    [0074] In a particular aspect, the charge value can be determined from the following formula:
    where LV = load value; RQ0 = a run queue value for core zero; IP0 = an inactive percentage for the zero core; UP0 = a percentage of utilization for the zero core; RQN = an execution queue value for the Nth nucleus; IPN = an inactive percentage for the Nésimo nucleus; and UPN = a percentage of utilization for the Nésimo core.
    [0075] In block 1420, one or more cores can be turned on or off based on the load value. It can be determined whether the charge value corresponds to a predetermined condition in order to determine whether to turn on or off one or more cores. For example, the load value can be compared to a limit and if the load value exceeds the limit, one or more cores can be turned on or off. For example, if there were two cores operating and the indicated load value of the two cores operating at or close to capacity, a third core can be connected and the workload can be dispersed between the three cores. Additionally, as the load value decreases below another limit indicating that it has a third operating core that is wasting energy, the third core can be shut down and the workload can be dispersed across the remaining two cores. In another aspect, the load value may indicate a current number of cores that must be running in order to provide the most efficient operation of the system.
    [0076] In a particular aspect, the controller can maintain historical data regarding the operation of the system and use historical data, the controller can implement a filter, for example, an IIR filter, the controller can implement an average motion function, or the controller can implement a combination of these. An average exemplary motion function is illustrated below: N = f (runQ0, run Q1, N1, N2, N3) = 2 if ((runQ0 + runQ1) + N1 + N2 + N3) / 4> 1, e = 1 if ((runQ0 + ruQ1) + N1 + N2 + N3) / 4 <= 1 where runQ0 = a run queue value for a zero core; runQ1 = a run queue value for a first core; and N1, N2, N3 = N values for the last three historical periods.
    [0077] It should be understood that the method steps described here do not necessarily have to be carried out in the order described. Additionally, the terms "later", "then", "next", etc. they should not limit the order of the stages. These words are simply used to guide the reader through the description of the method steps. In addition, the methods described here are described as executable on a portable computing device (PCD). The PCD can be a mobile phone device, a portable digital assistant device, a smartbook type computing device, a netbook type computing device, a laptop type computing device, a desktop type computing device, or a combination of these.
    [0078] With the configuration described here, the system and method described can reduce power consumption within a multi-core CPU by energizing additional CPU cores when there is the possibility of current acceleration due to workload parallelism. While the degree of parallelism may not be known in advance, the degree of parallelism can be inferred by looking at an execution queue length of the operating system programmer. Based on the degree of parallelism inferred, additional cores can be energized or de-energized when necessary.
    [0079] Unlike traditional systems, which energize all CPU cores symmetrically, that is, all on or off, the present system and method can energize and de-energize the CPU cores asymmetrically. In other words, one core can be energized while another is de-energized. In addition, as the workload increases and has sufficient parallelism, the second core can be energized.
    [0080] Additionally, the system and methods described here can dynamically adapt the number of energized cores to the current dynamic parallelism offered in the workload. This can save substantial energy. In addition, the system and method do not require developers to communicate the parallelism in their workloads in any special way. Applications may not need to be modified in any way and applications may be developed in a typical way. In addition, the present system and methods are compatible with existing applications and devices.
    [0081] In a particular aspect, the information for an MP controller is the number of ready-to-run sequences in the programmer's queue. It can be appreciated that other information that indicates parallelism in the workload can be used. However, an inactive / busy core indicator, which does not indicate parallelism, may not be enough information for the MP controller. For example, a CPU core may be 100% busy, but running on a single sequence workload. In this case, energizing the second core does not help the performance of the single sequence in any way. In fact, it can degrade performance by introducing the overhead required to power the second core. Worse, energizing a second core for a single sequence workload can introduce energy leakage with a large leak from the second core.
    [0082] Accordingly, in a particular aspect, it may be undesirable to energize the second core without guaranteeing that there is sufficient parallel work to do this. In an instant sense, working in parallel is only possible when there are two or more strings that are ready to run in the OS programmer's queues.
    [0083] In normal operation, in a dual-core example, the system can start with a DCVS algorithm operating on the zero CPU core, while a first CPU core remains dormant. In this mode, the system can respond to instantaneous transient loads by increasing the frequency of the CPU core to zero. The system can remain in single-core mode as long as there are insufficient ready-to-run sequences.
    [0084] However, once the ready-to-run limit Nw has been exceeded for a set amount of time, the zero CPU core can be implicitly saturated and there is also clearly a parallel workload available for the first core of CPU. A multi-core processor (MP) controller can invoke the OS to activate the first CPU core and add the first CPU core to the OS set of programmable resources. The MP controller can also start the first CPU core at the optimal frequency and voltage point, that is, the highest frequency at the lowest voltage, and activate the local DCVS for the first CPU core. The MP controller can optionally also reconfigure the frequency of the zero CPU core to the ideal frequency and voltage point. Otherwise, the MP controller may leave the CPU core frequency zero in the current configuration.
    [0085] Both cores can now operate with individually executed DCVS algorithms. With sustained parallel workloads, it may be likely that both cores will eventually reach the maximum frequency. However, there may be very brief slowdowns in the load that can allow the cores to partially decrease from the maximum frequency. However, such slowdowns are not possible without also reducing the number of strings that are ready to run to 0.
    [0086] Once enough slowdowns have occurred, causing the average number of ready-to-run sequences to fall below the Ns limit for a long enough duration, the MP controller can invoke the OS to save any suitable state from the first CPU core and remove it from its programmable set. Subsequently, the first CPU core can be safely de-energized. With the power of the first CPU core turned off, the system can return to a single core operating mode.
    [0087] In one or more illustrative aspects, the functions described can be implemented in hardware, software, firmware, or any combination of these. If implemented in software, functions can be stored in or transmitted as one or more instructions or code in a computer program product such as a machine-readable medium, that is, a computer-readable medium. The computer-readable medium includes both the computer storage medium and the communication medium including any medium that facilitates the transfer of a computer program from one place to another. A storage medium can be any available medium that can be accessed by a computer. By way of example, and not limitation, such a computer-readable medium may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store a desired program code in the form of instructions or data structures and which can be accessed by a computer. In addition, any connection is properly called a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies, such as infrared, radio and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. Disk and disk, as used here, include compact disk (CD), laser disk, optical disk, digital versatile disk (DVD), floppy disk and Blu-ray disk where disks normally reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included in the scope of computer-readable media.
    [0088] Although the selected aspects have been illustrated and described in detail, it will be understood that the various substitutions and changes can be made without departing from the inventive concept and scope of the present invention, as defined by the appended claims.
    权利要求:
    Claims (11)
    [0001]
    1. Method for dynamic energy control within a multi-core central processing unit (CPU), the method characterized by the fact that it comprises: receiving (910) a degree of parallelism in a zero-core workload (410 ), in which the degree of parallelism comprises a total number of tasks waiting in one or more queues ready for execution by an operating system programmer plus a number of tasks currently executing in core zero (410); determining (912) whether the degree of parallelism in the zero core workload (410) is equal to a first awakening condition, where the first awakening condition is satisfied when the degree of parallelism reaches or exceeds a threshold value; and energizing a first core (412) based at least in part on the degree of parallelism determined being equal to the first awakening condition and initially operating the zero core (410) and the first core (412) below an operational frequency and voltage point maximum.
    [0002]
    2. Method according to claim 1, characterized by the fact that it additionally comprises: determining (914) a length of time for which the first awakening condition is satisfied when the degree of parallelism in the zero core workload ( 410) is equal to the first awakening condition; and determining (916) whether the time duration is equal to a first confirmed awakening condition.
    [0003]
    3. Method according to claim 2, characterized by the fact that it further comprises: invoking (918) an operating system to energize the first core (412) when the time duration is equal to the first confirmed awakening condition.
    [0004]
    4. Method according to claim 3, characterized by the fact that it additionally comprises: invoking (920) the operating system to add the first core (412) to a set of programmable resources.
    [0005]
    5. Method, according to claim 4, characterized by the fact that it additionally comprises: receiving (1006) a degree of parallelism in a workload in the zero core (410) and the first core (412); and determining (1008) whether the degree of parallelism in the workload in the zero core (410) and the first core (412) is equal to a first resting condition.
    [0006]
    6. Method according to claim 5, characterized by the fact that it further comprises: determining (1010) a length of time for which the first resting condition is satisfied when the degree of parallelism in the workload in the zero core ( 410) and in the first nucleus (412) is equal to the first resting condition; and determining (1012) whether the length of time for which the first resting condition is satisfied is equal to a first confirmed resting condition.
    [0007]
    7. Method, according to claim 6, characterized by the fact that it additionally comprises: invoking (1014) the operating system to save the current state of the first core (412), when the length of time for which the first condition of rest is satisfied is equal to the first rest condition.
    [0008]
    8. Method according to claim 7, characterized by the fact that it additionally comprises: invoking (1016) the operating system to de-energize the first core (412).
    [0009]
    9. Method according to claim 8, characterized by the fact that it additionally comprises: invoking (1018) the operating system to remove the first core (412) from the set of programmable resources.
    [0010]
    10. Wireless device characterized by the fact that it comprises: mechanisms for receiving a degree of parallelism in a zero-core workload (410) from a multi-core central processing unit (402) of the wireless device, in which the degree of parallelism comprises a total number of tasks waiting in one or more queues ready for execution by an operating system programmer plus a number of tasks currently running at core zero (410); mechanisms for determining whether the degree of parallelism in the zero core workload (410) is equal to a first awakening condition, where the first awakening condition is satisfied when the degree of parallelism reaches or exceeds a threshold value; and mechanisms for energizing a first core (412) based at least in part on the degree of parallelism determined being equal to the first awakening condition and initially operating core zero (410) and the first core (412) below an operating point of maximum frequency and voltage.
    [0011]
    11. Computer-readable memory, characterized by the fact that it comprises instructions stored therein, the instructions being executable by a computer to perform the steps of the method as defined in any one of claims 1 to 9.
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    法律状态:
    2019-01-08| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2019-08-06| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2020-05-12| B06A| Notification to applicant to reply to the report for non-patentability or inadequacy of the application [chapter 6.1 patent gazette]|
    2020-07-21| B06I| Publication of requirement cancelled [chapter 6.9 patent gazette]|Free format text: ANULADA A PUBLICACAO CODIGO 6.1 NA RPI NO 2575 DE 12/05/2020 POR TER SIDO INDEVIDA. |
    2020-11-10| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2021-01-19| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 19/01/2021, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US28695309P| true| 2009-12-16|2009-12-16|
    US61/286,953|2009-12-16|
    US12/944,140|2010-11-11|
    US12/944,140|US9563250B2|2009-12-16|2010-11-11|System and method for controlling central processing unit power based on inferred workload parallelism|
    PCT/US2010/058075|WO2011084260A1|2009-12-16|2010-11-24|System and method for controlling central processing unit power based on inferred workload parallelism|
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